Panasonic and Renesas announce joint development of SoC process in Japan to increase efficiencies and improve the final product offering
Panasonic Corp and Renesas Technology have said they will concentrate their joint development functions for leading-edge SoC process technologies at the Renesas Naka site in Hitachinaka City, Japan, and planned to start operation of their 28nm to 32nm process development line installed at that site from October 1, 2009.
By carrying out this development in the wafer size that will actually be used in mass production, the two companies are aiming at achieving a smooth transition to mass production and reducing development costs and time. This will improve development and production efficiency. The 28nm to 32nm SoC process technologies that were the result of these joint development efforts have been applied in SoCs for leading-edge mobile applications and digital appliances from both companies. Full story via TechOn
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