Toshiba Corporation today announced its latest strategic roadmaps for the memory market, which reflect the company’s continued focus on the rapidly-growing file storage market, the mobile electronics memory market, and high-performance solutions for networking and digital consumer applications. This market segmentation enables Toshiba to respond rapidly to customer requirements and develop advanced memory solutions to meet their needs. Toshiba’s current line-up of memory products serving these three market segments includes NAND Flash, high-density NOR Flash, low-power SRAMs, Pseudo SRAMs (PSRAMs) and advanced Multi-Chip Packages (MCP) which integrate various memory technologies into a single package; and for the networking and extreme performance digital consumer market, Network Fast-Cycle RAMs (Network FCRAMs(TM)) and XDR(TM) DRAM.
File StorageNAND Flash memory continues to be one of the fastest growing semiconductor products, as continuing increases in density and improving cost per bit fuel strong demand for NAND Flash as a cost-effective memory choice for a wide range of file storage applications, including digital still and video cameras, USB drives, audio players, PDAs, solid-state disk drives, PC cards, and more.
Toshiba expects the market for NAND Flash to see 30 percent annual growth from CY2003 to CY2007, from 380-billion yen (approximately US$ 3.5-billion) to 1.2-trillion yen (approximately US$ 10.9-billion).
Toshiba recently announced that it is migrating NAND Flash production to 90-nanometer (nm) process technology, which enabled the company to introduce the industry’s first 4 gigabit (Gb) multi-level cell (MLC) NAND Flash memory, as well as a stacked, dual-die 8Gb device. These chips provide nearly twice the memory capacity of conventional chips of the same size by storingtwo bits per cell. Toshiba also developed faster MLC NAND Flash solutions by increasing the block size and optimizing the memory control function in the chips. By third quarter, Toshiba will bring a 16Gb MLC NAND Flash device to market by combining four 4Gb die in a single package.
To help meet the rapidly growing demand for NAND Flash, Toshiba started construction in April 2004 on a new $2.5 billion, 300 millimeter (mm) fab that is expected to come on line in the second half of fiscal 2005 with an initial output capacity of 10,000 wafers per month, growing to 37,500 wafers per month. Toshiba will fund construction of the building, and FlashVision Japan,a joint venture between Toshiba and its NAND Flash strategic partner, SanDisk Corp. (Nasdaq: SNDK), will fund its advanced manufacturing equipment, with each partner providing an equal share of the funds.
The roadmap for further lithography advances calls for mass production at 70nm to start in the first half of fiscal year 2005 at the existing 200mm fab, and in the first half of fiscal year 2006 at the new 300mm fab. Mass production of 55nm NAND Flash is scheduled to start in calendar year 2007 at the new fab.
For mobile electronics applications, Toshiba is one of the leading suppliers of MCPs, which combine various memory technologies in a single small-footprint component to meet the increasingly complex memory requirements of mobile devices. A key trend in MCP configurations is the inclusion of NAND Flash in addition to, or in place of, NOR Flash because of its significantlyfaster program and erase speeds which are necessary for fast data storage, especially in camera phones. Popular NAND Flash-based MCPs, which Toshiba also offers, include PSRAM+NOR+NAND and NAND+LPSDRAM.
To further reduce power consumption and improve memory subsystem performance in advanced 2.5G and 3G cell phones, Toshiba announced recently that it plans to offer a full 1.8V MCP device that incorporates burst mode NOR Flash, burst mode PSRAM, low-power SRAM, NAND and/or low power SDRAM. Typical configurations demanded include PSRAM+NOR, PSRAM+NOR+NAND,PSRAM+NOR+NAND+SDRAM or NAND+SDRAM.
Earlier this year, Toshiba announced development of an MCP with 1.4mm thickness that can stack 9 layers (for example, 6 memory chips with 3 spacers). Toshiba has utilized advanced process and mounting technology to shrink each memory chip to 70 micron thickness, the thinnest in the world for MCP applications, and then bond the chips together in one package by wires. The MCP consists of a combination of memory chips, such as SRAM, PSRAM, SDRAM, NOR Flash memory and NAND Flash memory. By using this technology, with a fewer number of chips stacked, it has also become possible to achieve an MCP with 1.0mm thickness. The chip combination available in these MCPs is flexible to accommodate the performance requirements of the customer and tocreate the most effective package.
Toshiba currently offers PSRAM in densities from 32 Megabit (Mb)3 up to 128Mb, the industry’s highest density of this low-power memory that has gained acceptance in cell phone applications, where the need for higher density working RAM is rapidly growing as more features and functions are implemented. PSRAM memory chips combine a DRAM cell for high density and low bit cost withan asynchronous SRAM external interface to facilitate efficient system design.
Toshiba’s burst PSRAM is based upon a common specification between Toshiba, NEC Electronics and Fujitsu for PSRAM devices that feature burst mode function enabling fast access operation. Each of the three companies independently manufactures and markets PSRAM products based on the common specification, called Common Specifications for Mobile RAM (COSMORAM). Toshiba recently announced a 1.8V 128Mb Burst Mode PSRAM for faster, low-voltage operation in next-generation cell phones.
Looking ahead, Toshiba will support up to 256Mb at 110nm in 2005.
As part of the recent announcement of a full 1.8V MCP solution, Toshiba is expanding its NOR Flash line-up with a 128Mb Page/Burst NOR Flash manufactured on a 130nm design rule. This device complements a selection of NOR Flash in 16Mb to 128Mb densities. The roadmap calls for higher density 256Mb and 512Mb products with the migration to 90nm process technology in 2005.
Low Power SRAM
Toshiba’s current low power SRAM line-up is manufactured on a 150nm design rule, with densities of 4Mb, 8Mb and 16Mb in various speeds and input voltages from 1.8V to 5V. The product roadmap calls for progression to 130nm in 2004.
- Networking/Digital Consumer
- Network FCRAM
For the communications market, Toshiba offers a family of Network FCRAM that combines DRAM densities with random cycle performance approaching that of high-speed SRAM to provide a cost-effective, high-performance solution for high-speed networking, routers, switches, and Internet servers. Network FCRAM features a short bus turnaround time, fast random access and cycle time, and a simple and consistent protocol, with a simplified command set. A variety ofproducts are now available from Toshiba, including 256Mb x8/x16 Network FCRAM1, 288Mb x18/x36 Network FCRAM2, and 512Mb x8/x16 Network FCRAM1.
Network FCRAM has been supported since end of 1999 and has enjoyed tremendous growth in design activity over the past year as a low cost, high performance replacement to high speed SRAM and DDR SDRAM for look-up table and buffer memory. Current devices are manufactured on a 130nm design rule and support random cycle times down to 20ns and data transfer rates up to 666Mbps. Next-generation devices will utilize a 110nm process and will offer higher data transfer rates and higher densities reaching 1.152Gb in 2006 at 90nm.
In late 2003, Toshiba was the first manufacturer to sample 512Mb XDR(TM) DRAMs with a data transfer speed of 3.2GHz, the world’s fastest speed of any memory device. These DRAMs are based on Rambus’ XDR memory interface technology and offer Octal Data Rates, which transfers eight data blocks per clock cycle and offers eight times the bandwidth of today’s best in class PCmemory. XDR DRAM is targeted for use in next-generation, high-performance broadband applications, including digital consumer electronics, network systems and graphic systems which are expected to require very high density, ultra-high-speed memory chips.
Toshiba’s initial product samples were developed on a 130nm process technology and shrink 110nm product is already under development for volume ramping in 2005. The company plans to migrate to a 90nm process in 2006, when the market for these emerging devices is expected to expand further.
(1) The US$ is valued at 110 yen for convenience only.
(2) When used herein, gigabit and/or Gb means 1,024X1,024X1,024 = 1,073,741,824 bits. Usable capacity may be less. For details, please refer to specifications.
(3) When used herein, megabit and Mb means 1,024X1,024 = 1,048,576 bits. Usable capacity may be less. For details, please refer to specifications.
Information in this press release, including product pricing and specifications, content of services and contact information, is current on the date of the announcement, but is subject to change without prior notice. Technical and application information contained here is subject to the most recent applicable Toshiba product specifications. In developing designs, please ensure that Toshiba products are used within specified operating ranges as set forth in the most recent Toshiba product specifications and theinformation set forth in Toshiba’s “Handling Guide for Semiconductor Devices,” or “Toshiba Semiconductor Reliability Handbook.”
This information is available at http://www.chips.toshiba.com